AnSem complements industry standard EDA tools with a proprietary EDA sizing tool and automation scripts. The Matlab based sizing program allows quick and efficient circuit design through a formal description of the sizing of transistors. All steps in the design flow are linked with Matlab and Python based scripts. Toplevel simulations at transistor level as well as with behavioral models, together with regression testing, with a goal of 100% simulation coverage across all corners , ensure AnSem’s first time functional success rate. Monte Carlo and circuit startup simulations on the backannotated netlist, together with EMC/EMI simulations and at speed digital testing can be added to the design to support the automotive goal of 0ppm over the lifetime of the IC.

• Cadence – Virtuoso for schematic entry and layout
• Spectre(RF) and Eldo(RF) and APS for analog, digital and mixed-signal simulations
• Cadence and Mentor based digital tools for simulation, synthesis, logic equivalence checking, timing closure, STA, formal verification, place-and-route and ATPG test pattern generation
• Extensive library of pCells
• Mentor Calibre for physical Verification (DRC/LVS) and parasitic extraction (xRC) and Analog FastSpice™ (AFS)
• VerilogA and VHDL AMS for analog behavioral modeling
• Cliosoft for version control
• Matlab (including custom toolboxes) and Simulink for concept definitions and system design
• Matlab and Python script-based control of the complete flow